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Interrupt Behaviour of the Z80 CPU

by Achim Flammenkamp

Interrupt timing

Only at the end of an instruction execution, except a NOP in case HALT, a LDD in case LDDR, a OUTI in case OTIR, etc., the CPU checks for an interrupt request. Thus the INT-pin should be active for at least 23 clock ticks because some IX resp. IY instruction last so long. Now an interrupt is accepted if INT-pin is low(active) and the interrupt flip flop IFF1 is set or the NMI-pin is respectively was active during the just performed instruction. If this is the case, the following happens:
Immediately IFF1 is reset to 0 and if INT-pin is low also IFF2 is reset to 0. Then the behavior depends whether it is a non maskable interrupt (NMI) or a maskable interrupt (INT). In the later case the interrupt mode (IM) of the CPU is also decisive: Some remarks:
  1. "acknowledge interrupt" means pin IORQ gets together with M1-pin active/low. Furthermore the CPU adds 2 wait states to the normal machine cycle.
  2. Quoted remark:
    • If a LD A,I or LD A,R (which copy IFF2 to the P/V flag) is interrupted, then the P/V flag is reset, even if interrupts were enabled beforehand.
    • If interrupts are disabled when a EI instruction is interrupted, then the interrupt will not occur until after the instruction following the EI, as when IFF1 is sampled during the one and only machine-cycle of the EI, it will be reset.
  3. An INT will let the INT-pin low(active) until it is indirectly reseted by an RETI or other external hardware. In contrast a signal at the NMI-pin will be recognized when its state going from high to low! Thus it is not a level trigger signal, but a pulse which is stored internally by the CPU until the next M1 cycle.

Reset Timing

One can consider a reset (RESET-pin gets low) as a very special interrupt. If this occurs, the following happens in one machine cycle:

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