Changes for Version 1.01

started with vme10 emulator version 1.0.13

added abillty of RWIN controller to access hard disks with sector sizes of 128, 512 and 1024 (already supported 256)  the RWIN driver knows nothing about it.. doon't need to specify sector size...automatically selects the size

added all disk formats described in IOS manual to RAW disk format table...described disks can be blank..all others must be formated

fixed LSN check for negative values..

fixed load disk to accept RAW files of any size < 2gb that have the VolID and CNG area defined. will set parameters according to the CNF area.  If parameters aren't right for device type..fails 

added cpu selection for 68030/010 Hybrid

NOTE - the BERR and AERR generate a 68010 stack format 8, not the 68030 format A and B. This allows Versados for the VME10 to work while in 68030/010 Hybrid cpu mode. 

NOTE - Also, the 68030 PMMU is NOT implemented. The system uses the 68451 BSMMU and still truncates the addresses to 24 bits. This allows Versados for the VME10 to work while in 68030/010 Hybrid cpu mode. 

added MSP, CACR, CAAR

added to SR bits T0, M. Trace on Flow (T0) is implemented in the MC engine

added to MOVEC support for MSP, ISP, CACR, CAAR

added Throw-a-way stack format and MSP / M bit support in Interrupt Exception Handler and in RTE 

added 68030 memory indirection support (used CPU32 microcode as base)

added ability to select default base to debugger

changed screen to not redraw a new pixel unless differnet than old pixel

added support for misaligned Word and Longword accesses
When CPU type is 68030/010hybrid, misaligned accesses are allowed
When CPU type is 68000, 68010, or CPU32/010hybrid, misaligned accesses are NOT allowed (Address Error Exception)

NOTE - all user resources  that access memory can do misaligned accesses, however supervisor resources such as Exceptions and RTE do not allow misaligned accesses. This means that the MSP and ISP must maintain even address alignment. As such, this means that a Throw-a-way stack that switches to the USP will fail if USP is odd. All other stack accesses can be odd. The RTS RTR RTD PEA BSR JSR and all accesses via (a7) can be odd. ( not PC... the A7 ) The Programmer MUST maintain even stack alignment for  ISP and MSP. Don't use odd alignment in supervisor mode on the stack-A7 ( MSP or ISP )

added BF instructions

added CAS and CAS2

added PACK and UNPK

