FILENAME: CIRCUITS.TXT   UPDATED 1-August-92 by Don McKenzie.
                   Ŀ
                    Circuits and Design Ideas 
                   
A collection of circuits and assembly instructions have been included
in the ZLOAD package that will greatly assist Z80 hardware designers.

Read MOREROM.DOC for additional information on this subject.

As is, the PBUFF board has no port decoding, so the 8255 responds to all
port addresses. Rom and Ram mapping is also very simple. Apart from the
Z80 signals themselves, no extra logic is used for Static ram address
decoding. The Dynamic ram uses the 74LS00 for decoding.

In order to decode the PBUFF 8255 to port zero, a 74LS138 can be used.
If this is done, capacitor C5 must be removed from the PBUFF board.

The following ports addresses are assigned for PBUFF use:

Port 00 to 0F  PBUFF 8255               ;PBUFF
Port 10 to 1F  LPT1: STROBE             ;C3P1
Port 20 to 2F  2ND   8255               ;C3P1
Port 30 to 3F  LPT2: STROBE             ;C3P1
Port 40 to 4F  WRITE Y0-Y7              ;C3P1
Port 50 to 5F  READ  X0-X7              ;C3P1
Port 60 to 6F  WRITE FPIO LEDS          ;FPIO
Port 70 to 7F  READ  FPIO SWITCHES      ;FPIO

The following memory addresses are assigned for PBUFF use:

0000 to 1FFF    2764 (8K) EPROM
2000 to 7FFF    3 Mirror images of EPROM.
8000 to 9FFF    6264 Static Ram
A000 to BFFF    Mirror image of Static ram
C000 to FFFF    Dynamic Ram usage.

The single Z80 address line A13 is used for the printer output strobe.
This signal has been inverted.

If A13 is high, strobe is low. Strobe asserted.
If A13 is low, strobe is high. No strobe.

A proposed internal serial port circuit has been included. Don't confuse
the purpose of this port with my serial board kit. This internal serial
port sits on the CPU bus. My serial board kit is only a serial to
parallel converter board, and it uses up 8255 ports, so they can't be
used for other functions.

Please excuse the rough circuit of the CPU bus serial port as it has
been patched together from four other circuits, and it's only four
chips, and yet to be proven.

The port addresses used conflict with my current C3P1 ports, so
adjustment would be required if these two circuits were used together.
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PBUFF 8255 Port C.

On the PBUFF CPU board, four port C 8255 signals don't connect to a
header pin. These are PC0 (8255/14), PC1 (8255/15), PC3 (8255/17), and
PC7 (8255/10). PC7 is also the Copy switch. 

These signals can easily be brought out by jumpering them on the solder
side of the board, to a socket installed into position Ey. A crimped DIP
header can then be used to continue these four signals on to your
project.

Five port C signals have 4K7 pullup resistors. These are PC2, PC4, PC5,
PC6, and PC7.

The pause pads must be jumpered to bring out PC6.
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40 pin extensions and multiple boards.

Multiple boards can be connected together by designing your circuits
around the PBUFF J1 header system. A flat ribbon cable with multiple 40
pin IDC headers crimped to it will do the job. This cable should be as
short as possible. Port and memory address conflicts have to be
regulated between boards. Ex could be used to jumper any extra decoding
signals if required.
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